Primary equipment in modern substations relies on digitized voltage and current measurements. Merging Units (MUs)—specialized physical devices installed in the switchyard that act like analog-to-digital translators by converting raw current and voltage wave signals into digital data streams—capture these physical inputs and publish them as Sampled Values over high-speed fiber-optic links. This process bus architecture replaces conventional point-to-point copper wiring, simplifying installation and reducing physical cable weight. However, this transition shifts the engineering focus to precise network timing. If the devices do not share a highly stable reference clock, sampling misalignment occurs. Time synchronization functions as the primary nervous system of the digital substation, directly protecting the grid from unscheduled trips.
Turkish Electricity Transmission Corporation (TEİAŞ), in collaboration with Hitachi Energy, is implementing Türkiye’s first digital substation pilot project. This initiative deploys IEC 61850 process bus technology by creating a parallel feeder control and protection bay that runs alongside the existing conventional system for comparative evaluation. The design deploys SAM600 Process Interface Units (PIUs) to realize Sampled Values (SV) and GOOSE communications, eliminating traditional copper cabling. Operating this parallel digital bay to evaluate its performance against conventional copper-based relays relies entirely on data packet alignment. Verifying that the digital process bus maintains absolute synchronization is a primary engineering requirement for comparative testing.
Conventional electromagnetic transformers send analog signals directly to protection relays via secondary cables. Because these electrical signals travel at nearly the speed of light without intermediate processing, current and voltage measurements are naturally synchronized.
In contrast, digital substations perform analog-to-digital conversion at the MU before transmitting packets over fiber optics. This distributed digitization process introduces deterministic and non-deterministic delays. Specifically, voltage signals must often pass through both a PT Merging Unit (for voltage transformers) and a Line Merging Unit (for feeder lines), accumulating two stages of hardware processing latency. Under these conditions, maintaining sampling alignment becomes challenging.
In a 50Hz grid, Merging Units output Sampled Values at a rate of 80 samples per cycle, yielding a time interval of 250µs between consecutive data points. Under these operating conditions, even microscopic time shifts lead to measurable errors. A synchronization discrepancy of only 1µs introduces approximately 1' of electrical phase angle error. When this timing drift increases to 5µs, it compromises the calculation accuracy of critical protection schemes.
Line differential protection compares current waveforms from remote ends of a transmission line. This method requires the measurements to be taken at the exact same instant. If the local and remote Merging Units experience a 5µs time difference, the differential relay calculates a false differential current. This error causes the protection to trip active lines under normal load.
Busbar protection also depends on simultaneous sampling across multiple circuits. A delay on a single feeder Merging Unit creates a false residual current calculation. This timing jitter can cause the busbar relay to fail to clear actual faults, or to trip falsely and shut down the entire substation. Distance relays also experience errors. Timing offsets distort the perceived impedance, causing the relay to miscalculate the fault distance and trip outside its designed zone.
Preventing false trips requires a two-step defense. The first step uses satellite hardware for normal operations. The second step uses software calculations as a backup.
In the hardware step, master clocks receive timing signals from GPS and Beidou satellites. To align the measurements, all Merging Units wait for a pre-set time after capturing the current. After this brief wait, they transmit their Sampled Values at the exact same moment. The protection relays then read the time stamp inside each data packet. If a small timing difference remains, the relay adjusts its calculations to compensate for the phase angle error.
This time stamp must be marked by network hardware chips rather than computer software. Software timing protocols like NTP (Network Time Protocol)—a common software-only protocol used to synchronize clocks on standard IT computers over network connections—are too slow for electrical protection. NTP suffers from random delays of up to several milliseconds because it depends on the computer processor, which might be busy with other tasks. Hardware timestamping records the time at the physical network chip (PHY layer) the exact microsecond a packet arrives. This physical layer method removes computer processing delays, keeping the synchronization error under 1µs.
Software synchronization provides logical backup capability during timing network failures. If satellite antennas fail, the master clock loses its connection and enters a drift state. To prevent the relays from tripping instantly, the system starts a calculation method called interpolation. Using Lagrange or Spline algorithms, the protection devices calculate virtual values for missing sampling points based on previous data. This software interpolation keeps the protection functional, allowing the station to operate safely while maintenance crews restore the physical timing source.
Verifying this 5µs synchronization limit under actual operating conditions requires precise field testing. Commissioning teams must test the system according to the IEC 61850-9-2 and IEC 61869 standards, which define the required timing margins.
Testing engineers use specialized portable test sets to inject physical and digital signals simultaneously. Portable testers from KINGSINE, such as the KF86P, are designed for this task. The test set connects directly to the fiber-optic network. It publishes Sampled Values and GOOSE packets while subscribing to the Merging Unit output.
To perform end-to-end testing, engineers place one tester at the local terminal and another at the remote terminal. Both testers synchronize their internal clocks using integrated GPS and Beidou modules. The units inject identical, time-synchronized current waveforms at both ends of the line. This method allows engineers to measure the absolute timing accuracy of the Merging Units and observe the relay reaction under controlled delay conditions.
Traditional testing tools often focus on bench calibration, making them bulky for field environments. KINGSINE test sets provide a compact, integrated interface that simplifies the verification of the digital process bus, offering a practical tool for modern grid commissioning.
Digital substations offer deep visibility into power grid performance, but they rely entirely on precise time alignment. Validating the 5µs synchronization boundary is essential to prevent false trips on critical protection schemes. Through hybrid interfaces, KINGSINE enables testing engineers to verify these digital timing links.
The equipment supports IRIG-B—a highly stable timing standard that transmits serial time codes over dedicated physical cables, bypassing the network stack to eliminate any queuing delay—ensuring compatibility with legacy substations.
Additionally, the testers support IEEE 1588 PTP (Precision Time Protocol)—a highly precise network-based timing standard that utilizes hardware timestamping on the physical network chip to achieve sub-microsecond synchronization over standard Ethernet. This dual-protocol verification capability ensures that testing engineers can safeguard the modern power grid under all operating conditions.
If the master satellite clock loses GPS/Beidou signals, the system enters a "holdover" state relying on its internal oscillator. To prevent false protection trips due to immediate time drift, modern relays instantly activate software interpolation algorithms. These algorithms use mathematical methods (such as Lagrange interpolation) to calculate virtual aligned sampling values. This allows the system to remain safely online for a limited time until technicians restore the hardware timing source.
NTP is a software-only protocol running in the computer operating system layer. Because its packet processing is subject to operating system task scheduling and processor queues, it introduces random delays of up to several milliseconds. Electrical protection schemes require sub-microsecond synchronization. This can only be achieved via hardware timestamping, where network physical chipsets (PHY layer) record the packet timing instantly on the wire, bypassing all software jitter.
Voltage signals in digital substations often pass through both a PT Merging Unit and a Line Merging Unit, introducing two stages of processing latency. Without synchronization, these multi-stage hardware delays distort the phase relationship between current and voltage. This distortion introduces phase angle errors that directly degrade the accuracy of active power metering, power quality monitoring, and impedance-based distance relay zones.
English 
日本語 
français 
Deutsch 
Español 
italiano 
русский 
português 
العربية 
Polska 
